With high-integration and miniaturization of semiconductor devices, techniques that form buried source/drain regions by forming a recessed portion in source/drain forming regions and forming a semiconductor layer in the recessed portion by crystal growth are disclosed in Japanese Laid-open Patent Publication Nos. 2006-319326, 2008-047586, and 2003-243532 etc.
In a p-channel MOSFET, enhancing performance of a transistor is proposed in which compressive stress is applied to a channel region by epitaxially grown a SiGe layer in source/drain regions. As a countermeasure for junction capacity in a p-channel MOSFET, Japanese Laid-open Patent Publication No. 2006-319236 discloses that implanting Boron (B) to a semiconductor substrate to form a p-type diffusion region with a concentration of approximately 1×1018 cm−3 before a SiGe layer is epitaxially grown.
On the other hand, in an n-channel MOSFET, burying a SiGeC layer in source/drain regions is proposed in Japanese Laid-open Patent Publication No. 2003-243532.
FIG. 9 is a sectional view of a major portion of a MOSFET including a SiGe source/drain. A gate insulating film 82 and a gate electrode 83 are formed over an n-type well region 81, a sidewall 84 is formed, and a p-type extension region 85 is formed. A p-type diffusion region 87 is formed in order to reduce junction capacity after forming a sidewall 86.
A trench portion is formed by etching source/drain forming regions and a p-type SiGe layer 88 is epitaxially grown in the trench portion.